Results

Minimum Energy Point

We compute the minimum energy point in terms of the supply voltage to be used, for various process technologies. The following graph describes the trends in optimal supply voltage over different process nodes.

_images/results-1.png

UMC 180nm CMOS

Transistor sizing was done in the conventional method, matching push-up and pull-down currents. All pull-down paths with a single transistor had a minimum sized nMOS.

Initially, a 32-bit ALU was synthesized with sub-vt standard cells in 180nm CMOS. The following tabulation describes power and delay results in the same.

_images/alu-results.png

UMC 65nm CMOS

The minimum energy point was obtained for an inverter with sizing for symmetric operation.

_images/umc65ll.png

An inverter was designed and it’s sizing was optimized using SpectreMDL.

_images/umc65-opt.png

UMC 40nm CMOS

The minimum energy point was obtained for an inverter with sizing for symmetric operation.

_images/umc40lp.png

An inverter was designed and it’s sizing was optimized using SpectreMDL.

_images/L40_INV.png

We try to further reduce the energy consumption of the inverter by increasing the weights in optimization.

_images/L40_INV_E1.png

After plotting the entire set of solutions obtained during optimization as intermediate results, we obtain the following scatter plot. The red points are the 2 extreme solutions in terms of energy and delay.

_images/scatter.png

Upon selecting the right weights for optimisation, and an initial point that is supportive of the solver’s method, energy efficiency can be obtained.

UMC 28nm CMOS

The following plots describe the variation in static and dynamic energy over a range of supply voltages.

_images/umc28hpc.png

Power, Delay and Energy were plotted for a varying supply voltage.

_images/delay-power-energy.png _images/pareto-28.png

Chromite RV32IMFC was synthesized using UMC 28nm at 2 design goals (supply voltage), 180 mV and 300 mV _without_ any optimization for sizing. The following table describes the synthesis results for the same.

_images/chromite-28nm.png

The following microarchitectural changes were made to the core:

  1. mul_stages = (2, 4, 6)

  2. isb_size (per stage) = 2,2,1,8,8 -> 4,4,1,16,16

Energy was plotted against execution time for benchmarks from Embench-IoT.

_images/subvt-chromite-matlab.png

Frequency, Power, and Energy were ploted for Chromite RISC-V.

_images/color-freq.png _images/color-power.png _images/color-energy.png

To understand the maximum operating speeds in sub-threshold, the largest possible cells (with 1 finger) were characterized. The following table describes the results obtained using these cells for a 32-bit ALU.

_images/alu-large.png

Warning

I have not synthesized any designs in 28nm CMOS post the transistor sizing, as optimization itself is still a work in progress.

Standard cell sizing has to be optimized such that the energy consumption is below that of super-threshold synthesis.