Welcome to our documentation!

Abstract

In the present era of high-density and high-speed nanoelectronics, energy consumption has been one of the most concerning factors. Hence there is a rapidly growing demand for ultra-low power devices and advanced energy-saving methods for digital integrated circuits primarily because of the growing need for portability in computing and telecommunication products. We design standard cells to be used in a semi-custom ASIC Design flow. We further reduce the energy consumption of UMC’s commercial 28nm High-Performance Compact CMOS Process Technology by down-scaling the supply voltage. We automate significant parts of the logic gate design process, enabling the rapid adoption of new processes or alternative designs.

Project contributors

Karthik B K <bkkarthik@pesu.pes.edu> Prof. Vinay Reddy <vinay@pes.edu> Dr. Madhura Purnaprajna <madhurap@pes.edu>

Learn more

https://chips.pes.edu/projects

Note

This project is under active development.

• Theory
  • Structure of a MOSFET
  • Regions of Operation
  • CMOS Logic Gates
• Design Flow
  • Choosing Transistor Variant
  • Schematic Generation
  • Computing the Optimal Supply voltage
  • Transistor Sizing
  • Layout Generation
  • Netlist Extraction
  • Cell Characterization
  • Synthesis
  • Post-Synthesis Simulation
• Results
  • Minimum Energy Point
  • UMC 180nm CMOS
  • UMC 65nm CMOS
  • UMC 40nm CMOS
  • UMC 28nm CMOS
• References
  • Relevant links